The present invention relates generally to phase locked loop (PLL) circuits used in various communication receivers, and more specifically to a method and apparatus for cancelling phase jitter in a PLL circuit.
A phase locked loop (PLL) is a circuit that allows a particular system to track with another one. More to the point, a PLL is a circuit that synchronizes an output signal (generated by an oscillator) with an input, or reference, signal in frequency and phase. Ideally, when the PLL is operating in the synchronized, or `locked`, state the difference in phase between the oscillator's output signal and the reference signal is zero. In other words, the phase of the output signal is `locked` to the phase of the reference signal.
FIG. 1 is a block diagram of a conventional PLL circuit 200. The PLL circuit 200 includes a phase detector 210, a low pass filter 220, and a voltage controlled oscillator (VCO) 230. The phase detector is a device that compares the frequency and phase of two input signals, a reference signal/frequency (f.sub.in) and the output signal/frequency of the VCO (f.sub.vco), and generates an output that is the measure of their phase difference (f.sub.in -f.sub.vco). The output of the phase detector is filtered, amplified and input to the VCO. If f.sub.vco is not equal to f.sub.in the phase error signal causes the VCO output frequency to deviate in the direction of f.sub.in. If conditions are just right, the VCO will lock in to f.sub.in, and a fixed phase relationship with the input reference signal will be established.
In communication systems, PLLs are used extensively for applications including tone decoding, demodulation of AM and FM signals, and regeneration of clean signals. One important capability of the PLL is its ability to suppress noise superimposed on its input signal. The phase detector will try to measure the phase error between the input and output signals, but the phase jitter at the input will cause the zero crossings of a sinusoidal input signal to be advanced or delayed. This causes the phase detector output signal to jitter around an average value. Such phase jitter, if large enough, could potentially `unlock` the system or introduce errors in a communications system by moving received data points across decision boundaries. It is therefore desirable to filter out or cancel any phase jitter in the PLL system. Phase jitter is a common impairment encountered in real world communications systems, and particularly in systems communicating over voice telephone lines. Of particular importance is the impairment of communication capabilities due to phase jitter in modems operating over voice telephone lines with a large number of points in their constellations, such as a V.17 modem. Phase jitter is typically generated by noise in networks and by poor power supplies.
Most previous methods have utilized an LMS-based adaptive filter approach wherein a filter, such as a finite impulse response filter (FIR), is forced into a configuration that cancels the phase jitter. This approach, however, is a complex approach requiring significant computational resources as well as significant amounts of memory.
As is evident from the above, there is need in the art for a simple, cost-effective method for cancelling phase jitter, with low memory and computational resource requirements.